nBitAddSub1 Project Status (05/19/2016 - 13:55:23)
Project File: nBitAddSub1.xise Parser Errors: No Errors
Module Name: nBitAddSub1 Implementation State: Placed and Routed
Target Device: xc6slx9-3tqg144
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 0 11,440 0%  
Number of Slice LUTs 6 5,720 1%  
    Number used as logic 6 5,720 1%  
        Number using O6 output only 3      
        Number using O5 output only 0      
        Number using O5 and O6 3      
        Number used as ROM 0      
    Number used as Memory 0 1,440 0%  
Number of occupied Slices 2 1,430 1%  
Number of MUXCYs used 0 2,860 0%  
Number of LUT Flip Flop pairs used 6      
    Number with an unused Flip Flop 6 6 100%  
    Number with an unused LUT 0 6 0%  
    Number of fully used LUT-FF pairs 0 6 0%  
    Number of slice register sites lost
        to control set restrictions
0 11,440 0%  
Number of bonded IOBs 15 102 14%  
    Number of LOCed IOBs 15 15 100%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 0 16 0%  
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 0 200 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 2.06      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent格 5 19 13:54:50 2016000
Translation ReportCurrent格 5 19 13:54:56 2016000
Map ReportCurrent格 5 19 13:55:04 2016006 Infos (0 new)
Place and Route ReportCurrent格 5 19 13:55:12 2016002 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrent格 5 19 13:55:16 2016004 Infos (0 new)
Bitgen ReportOut of Date格 5 19 11:58:22 2016000
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrent格 5 19 13:55:42 2016
Post-Place and Route Simulation Model ReportCurrent格 5 19 13:55:22 2016
WebTalk ReportOut of Date格 5 19 11:58:24 2016
WebTalk Log FileOut of Date格 5 19 11:58:28 2016

Date Generated: 12/10/2016 - 18:04:06