nBitAddSub1 Project Status (05/19/2016 - 13:55:23) | |||
Project File: | nBitAddSub1.xise | Parser Errors: | No Errors |
Module Name: | nBitAddSub1 | Implementation State: | Placed and Routed |
Target Device: | xc6slx9-3tqg144 |
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No Errors |
Product Version: | ISE 14.7 |
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No Warnings |
Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Slice Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Registers | 0 | 11,440 | 0% | ||
Number of Slice LUTs | 6 | 5,720 | 1% | ||
Number used as logic | 6 | 5,720 | 1% | ||
Number using O6 output only | 3 | ||||
Number using O5 output only | 0 | ||||
Number using O5 and O6 | 3 | ||||
Number used as ROM | 0 | ||||
Number used as Memory | 0 | 1,440 | 0% | ||
Number of occupied Slices | 2 | 1,430 | 1% | ||
Number of MUXCYs used | 0 | 2,860 | 0% | ||
Number of LUT Flip Flop pairs used | 6 | ||||
Number with an unused Flip Flop | 6 | 6 | 100% | ||
Number with an unused LUT | 0 | 6 | 0% | ||
Number of fully used LUT-FF pairs | 0 | 6 | 0% | ||
Number of slice register sites lost to control set restrictions |
0 | 11,440 | 0% | ||
Number of bonded IOBs | 15 | 102 | 14% | ||
Number of LOCed IOBs | 15 | 15 | 100% | ||
Number of RAMB16BWERs | 0 | 32 | 0% | ||
Number of RAMB8BWERs | 0 | 64 | 0% | ||
Number of BUFIO2/BUFIO2_2CLKs | 0 | 32 | 0% | ||
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% | ||
Number of BUFG/BUFGMUXs | 0 | 16 | 0% | ||
Number of DCM/DCM_CLKGENs | 0 | 4 | 0% | ||
Number of ILOGIC2/ISERDES2s | 0 | 200 | 0% | ||
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 200 | 0% | ||
Number of OLOGIC2/OSERDES2s | 0 | 200 | 0% | ||
Number of BSCANs | 0 | 4 | 0% | ||
Number of BUFHs | 0 | 128 | 0% | ||
Number of BUFPLLs | 0 | 8 | 0% | ||
Number of BUFPLL_MCBs | 0 | 4 | 0% | ||
Number of DSP48A1s | 0 | 16 | 0% | ||
Number of ICAPs | 0 | 1 | 0% | ||
Number of MCBs | 0 | 2 | 0% | ||
Number of PCILOGICSEs | 0 | 2 | 0% | ||
Number of PLL_ADVs | 0 | 2 | 0% | ||
Number of PMVs | 0 | 1 | 0% | ||
Number of STARTUPs | 0 | 1 | 0% | ||
Number of SUSPEND_SYNCs | 0 | 1 | 0% | ||
Average Fanout of Non-Clock Nets | 2.06 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | 格 5 19 13:54:50 2016 | 0 | 0 | 0 | |
Translation Report | Current | 格 5 19 13:54:56 2016 | 0 | 0 | 0 | |
Map Report | Current | 格 5 19 13:55:04 2016 | 0 | 0 | 6 Infos (0 new) | |
Place and Route Report | Current | 格 5 19 13:55:12 2016 | 0 | 0 | 2 Infos (0 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | 格 5 19 13:55:16 2016 | 0 | 0 | 4 Infos (0 new) | |
Bitgen Report | Out of Date | 格 5 19 11:58:22 2016 | 0 | 0 | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Current | 格 5 19 13:55:42 2016 | |
Post-Place and Route Simulation Model Report | Current | 格 5 19 13:55:22 2016 | |
WebTalk Report | Out of Date | 格 5 19 11:58:24 2016 | |
WebTalk Log File | Out of Date | 格 5 19 11:58:28 2016 |