nBitAddSub2 Project Status
Project File: nBitAddSub2.xise Parser Errors: No Errors
Module Name: nBitAddSub2 Implementation State: Programming File Generated
Target Device: xc6slx9-3tqg144
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 33 11,440 1%  
    Number used as Flip Flops 33      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 92 5,720 1%  
    Number used as logic 91 5,720 1%  
        Number using O6 output only 49      
        Number using O5 output only 30      
        Number using O5 and O6 12      
        Number used as ROM 0      
    Number used as Memory 0 1,440 0%  
    Number used exclusively as route-thrus 1      
        Number with same-slice register load 0      
        Number with same-slice carry load 1      
        Number with other load 0      
Number of occupied Slices 30 1,430 2%  
Number of MUXCYs used 40 2,860 1%  
Number of LUT Flip Flop pairs used 92      
    Number with an unused Flip Flop 59 92 64%  
    Number with an unused LUT 0 92 0%  
    Number of fully used LUT-FF pairs 33 92 35%  
    Number of unique control sets 2      
    Number of slice register sites lost
        to control set restrictions
7 11,440 1%  
Number of bonded IOBs 28 102 27%  
    Number of LOCed IOBs 28 28 100%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 0 200 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 2.44      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent¼ö 11 25 15:12:43 2015000
Translation ReportCurrent¼ö 11 25 15:12:48 2015000
Map ReportCurrent¼ö 11 25 15:12:55 2015006 Infos (0 new)
Place and Route ReportCurrent¼ö 11 25 15:13:01 2015003 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrent¼ö 11 25 15:13:06 2015004 Infos (0 new)
Bitgen ReportCurrent¼ö 11 25 15:13:13 2015000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrent¼ö 11 25 15:17:52 2015
WebTalk Log FileCurrent¼ö 11 25 15:17:56 2015

Date Generated: 01/06/2016 - 17:55:51