Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx9
Project ID (random number) 173d2d9871ea4b1a9eb4f82a81cba1d7.C767F347BC004877BB142E62D9B0648E.5 Target Package: tqg144
Registration ID 176499477_176905455_0_416 Target Speed: -3
Date Generated 2016-05-29T21:09:34 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i5-3470 CPU @ 3.20GHz CPU Speed 3192 MHz
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i5-3470 CPU @ 3.20GHz CPU Speed 3192 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Comparators=1
  • 32-bit comparator greater=1
Counters=1
  • 32-bit up counter=1
Registers=3
  • Flip-Flops=3
MiscellaneousStatistics
  • AGG_BONDED_IO=4
  • AGG_IO=4
  • AGG_LOCED_IO=4
  • AGG_SLICE=21
  • NUM_BONDED_IOB=4
  • NUM_BSFULL=34
  • NUM_BSLUTONLY=39
  • NUM_BSREGONLY=1
  • NUM_BSUSED=74
  • NUM_BUFG=1
  • NUM_LOCED_IOB=4
  • NUM_LOGIC_O5ANDO6=8
  • NUM_LOGIC_O5ONLY=30
  • NUM_LOGIC_O6ONLY=34
  • NUM_LUT_RT_DRIVES_CARRY4=1
  • NUM_LUT_RT_EXO6=1
  • NUM_LUT_RT_O6=30
  • NUM_SLICEL=10
  • NUM_SLICEX=11
  • NUM_SLICE_CARRY4=10
  • NUM_SLICE_CONTROLSET=4
  • NUM_SLICE_CYINIT=113
  • NUM_SLICE_FF=35
  • NUM_SLICE_UNUSEDCTRL=10
  • NUM_UNUSABLE_FF_BELS=21
NetStatistics
  • NumNets_Active=85
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=4
  • NumNodesOfType_Active_BOUNCEIN=8
  • NumNodesOfType_Active_BUFGOUT=1
  • NumNodesOfType_Active_BUFHINP2OUT=2
  • NumNodesOfType_Active_CLKPIN=11
  • NumNodesOfType_Active_CLKPINFEED=2
  • NumNodesOfType_Active_CNTRLPIN=3
  • NumNodesOfType_Active_DOUBLE=37
  • NumNodesOfType_Active_GENERIC=6
  • NumNodesOfType_Active_GLOBAL=13
  • NumNodesOfType_Active_INPUT=9
  • NumNodesOfType_Active_IOBIN2OUT=3
  • NumNodesOfType_Active_IOBOUTPUT=3
  • NumNodesOfType_Active_LUTINPUT=133
  • NumNodesOfType_Active_OUTBOUND=73
  • NumNodesOfType_Active_OUTPUT=79
  • NumNodesOfType_Active_PADINPUT=1
  • NumNodesOfType_Active_PADOUTPUT=3
  • NumNodesOfType_Active_PINBOUNCE=34
  • NumNodesOfType_Active_PINFEED=148
  • NumNodesOfType_Active_QUAD=20
  • NumNodesOfType_Active_REGINPUT=2
  • NumNodesOfType_Active_SINGLE=84
  • NumNodesOfType_Vcc_HVCCOUT=11
  • NumNodesOfType_Vcc_LUTINPUT=38
  • NumNodesOfType_Vcc_PINFEED=38
SiteStatistics
  • BUFG-BUFGMUX=1
  • IOB-IOBM=1
  • IOB-IOBS=3
  • SLICEL-SLICEM=8
  • SLICEX-SLICEM=2
SiteSummary
  • BUFG=1
  • BUFG_BUFG=1
  • CARRY4=10
  • FF_SR=1
  • HARD0=1
  • HARD1=1
  • INVERTER=1
  • IOB=4
  • IOB_IMUX=3
  • IOB_INBUF=3
  • IOB_OUTBUF=1
  • LUT5=38
  • LUT6=73
  • PAD=4
  • REG_SR=34
  • SLICEL=10
  • SLICEX=11
 
Configuration Data
FF_SR
  • CK=[CK:1] [CK_INV:0]
  • SRINIT=[SRINIT0:1]
  • SYNC_ATTR=[SYNC:1]
IOB_OUTBUF
  • DRIVEATTRBOX=[12:1]
  • SLEW=[SLOW:1]
  • SUSPEND=[3STATE:1]
REG_SR
  • CK=[CK:34] [CK_INV:0]
  • LATCH_OR_FF=[FF:34]
  • SRINIT=[SRINIT0:34]
  • SYNC_ATTR=[ASYNC:34]
SLICEX
  • CLK=[CLK:11] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=1
  • O=1
BUFG_BUFG
  • I0=1
  • O=1
CARRY4
  • CIN=8
  • CO2=1
  • CO3=8
  • CYINIT=2
  • DI0=10
  • DI1=10
  • DI2=10
  • DI3=8
  • O0=8
  • O1=8
  • O2=8
  • O3=8
  • S0=10
  • S1=10
  • S2=10
  • S3=9
FF_SR
  • CK=1
  • D=1
  • Q=1
  • SR=1
HARD0
  • 0=1
HARD1
  • 1=1
INVERTER
  • IN=1
  • OUT=1
IOB
  • I=3
  • O=1
  • PAD=4
IOB_IMUX
  • I=2
  • I_B=1
  • OUT=3
IOB_INBUF
  • OUT=3
  • PAD=3
IOB_OUTBUF
  • IN=1
  • OUT=1
LUT5
  • A1=4
  • A2=5
  • A3=5
  • A4=6
  • A5=5
  • O5=38
LUT6
  • A1=5
  • A2=6
  • A3=6
  • A4=9
  • A5=71
  • A6=72
  • O6=73
PAD
  • PAD=4
REG_SR
  • CE=1
  • CK=34
  • D=34
  • Q=34
  • SR=1
SLICEL
  • A1=2
  • A2=2
  • A3=2
  • A4=2
  • A5=10
  • A6=10
  • AMUX=8
  • B1=2
  • B2=2
  • B3=2
  • B4=2
  • B5=10
  • B6=10
  • BMUX=8
  • C1=1
  • C2=1
  • C3=1
  • C4=2
  • C5=10
  • C6=10
  • CIN=8
  • CMUX=9
  • COUT=8
  • D2=1
  • D3=1
  • D4=1
  • D5=8
  • D6=9
  • DMUX=8
  • DX=1
SLICEX
  • A=1
  • A2=1
  • A3=1
  • A4=1
  • A5=9
  • A6=9
  • AMUX=1
  • AQ=9
  • AX=1
  • B5=8
  • B6=8
  • BQ=8
  • C5=8
  • C6=8
  • CE=1
  • CLK=11
  • CQ=8
  • D4=1
  • D5=8
  • D6=8
  • DQ=9
  • SR=2
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 18 18 0 0 0 0 0
bitgen 172 172 0 0 0 0 0
map 178 172 0 0 0 0 0
netgen 8 8 0 0 0 0 0
ngdbuild 188 188 0 0 0 0 0
par 172 172 0 0 0 0 0
trce 171 171 0 0 0 0 0
xst 250 250 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2015-10-04T08:37:22
PROP_intWbtProjectID=C767F347BC004877BB142E62D9B0648E PROP_intWbtProjectIteration=5
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=true
PROP_DevFamily=Spartan6 PROP_DevDevice=xc6slx9
PROP_DevFamilyPMName=spartan6 PROP_DevPackage=tqg144
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-3
PROP_PreferredLanguage=Verilog FILE_UCF=1
FILE_VHDL=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=32 NGDBUILD_NUM_FDC=1 NGDBUILD_NUM_FDE=1
NGDBUILD_NUM_FDR=1 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=2 NGDBUILD_NUM_INV=3
NGDBUILD_NUM_LUT1=31 NGDBUILD_NUM_LUT2=35 NGDBUILD_NUM_LUT3=1 NGDBUILD_NUM_LUT5=10
NGDBUILD_NUM_MUXCY=38 NGDBUILD_NUM_OBUF=1 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=32
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=32 NGDBUILD_NUM_FDC=1 NGDBUILD_NUM_FDE=1
NGDBUILD_NUM_FDR=1 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=2 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=3 NGDBUILD_NUM_LUT1=31 NGDBUILD_NUM_LUT2=35 NGDBUILD_NUM_LUT3=1
NGDBUILD_NUM_LUT5=10 NGDBUILD_NUM_MUXCY=38 NGDBUILD_NUM_OBUF=1 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=32
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx9-3-tqg144
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5