timeSetPosition Project Status | |||
Project File: | timeSetPosition.xise | Parser Errors: | No Errors |
Module Name: | timeSetPosition | Implementation State: | Programming File Generated |
Target Device: | xc6slx9-3tqg144 |
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No Errors |
Product Version: | ISE 14.7 |
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1 Warning (1 new) |
Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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All Constraints Met |
Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Slice Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Registers | 3 | 11,440 | 1% | ||
Number used as Flip Flops | 3 | ||||
Number used as Latches | 0 | ||||
Number used as Latch-thrus | 0 | ||||
Number used as AND/OR logics | 0 | ||||
Number of Slice LUTs | 0 | 5,720 | 0% | ||
Number of occupied Slices | 1 | 1,430 | 1% | ||
Number of MUXCYs used | 0 | 2,860 | 0% | ||
Number of LUT Flip Flop pairs used | 3 | ||||
Number with an unused Flip Flop | 0 | 3 | 0% | ||
Number with an unused LUT | 3 | 3 | 100% | ||
Number of fully used LUT-FF pairs | 0 | 3 | 0% | ||
Number of unique control sets | 1 | ||||
Number of slice register sites lost to control set restrictions |
5 | 11,440 | 1% | ||
Number of bonded IOBs | 5 | 102 | 4% | ||
Number of LOCed IOBs | 5 | 5 | 100% | ||
Number of RAMB16BWERs | 0 | 32 | 0% | ||
Number of RAMB8BWERs | 0 | 64 | 0% | ||
Number of BUFIO2/BUFIO2_2CLKs | 0 | 32 | 0% | ||
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% | ||
Number of BUFG/BUFGMUXs | 1 | 16 | 6% | ||
Number used as BUFGs | 1 | ||||
Number used as BUFGMUX | 0 | ||||
Number of DCM/DCM_CLKGENs | 0 | 4 | 0% | ||
Number of ILOGIC2/ISERDES2s | 0 | 200 | 0% | ||
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 200 | 0% | ||
Number of OLOGIC2/OSERDES2s | 0 | 200 | 0% | ||
Number of BSCANs | 0 | 4 | 0% | ||
Number of BUFHs | 0 | 128 | 0% | ||
Number of BUFPLLs | 0 | 8 | 0% | ||
Number of BUFPLL_MCBs | 0 | 4 | 0% | ||
Number of DSP48A1s | 0 | 16 | 0% | ||
Number of ICAPs | 0 | 1 | 0% | ||
Number of MCBs | 0 | 2 | 0% | ||
Number of PCILOGICSEs | 0 | 2 | 0% | ||
Number of PLL_ADVs | 0 | 2 | 0% | ||
Number of PMVs | 0 | 1 | 0% | ||
Number of STARTUPs | 0 | 1 | 0% | ||
Number of SUSPEND_SYNCs | 0 | 1 | 0% | ||
Average Fanout of Non-Clock Nets | 2.00 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | ¼ö 3 30 22:31:46 2016 | 0 | 0 | 0 | |
Translation Report | Current | ¼ö 3 30 22:32:50 2016 | 0 | 0 | 0 | |
Map Report | Current | ¼ö 3 30 22:32:57 2016 | 0 | 1 Warning (1 new) | 6 Infos (1 new) | |
Place and Route Report | Current | ¼ö 3 30 22:33:05 2016 | 0 | 0 | 3 Infos (3 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | ¼ö 3 30 22:33:11 2016 | 0 | 0 | 4 Infos (4 new) | |
Bitgen Report | Current | ¼ö 3 30 22:33:19 2016 | 0 | 0 | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Current | ¼ö 3 30 22:35:45 2016 | |
WebTalk Log File | Current | ¼ö 3 30 22:35:50 2016 |