DigitalWatch Project Status (04/04/2016 - 17:45:24)
Project File: DigitalWatch.xise Parser Errors: No Errors
Module Name: DigitalWatch Implementation State: Programming File Generated
Target Device: xc6slx9-3tqg144
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
49 Warnings (49 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 152 11,440 1%  
    Number used as Flip Flops 152      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 273 5,720 4%  
    Number used as logic 270 5,720 4%  
        Number using O6 output only 153      
        Number using O5 output only 44      
        Number using O5 and O6 73      
        Number used as ROM 0      
    Number used as Memory 0 1,440 0%  
    Number used exclusively as route-thrus 3      
        Number with same-slice register load 0      
        Number with same-slice carry load 3      
        Number with other load 0      
Number of occupied Slices 103 1,430 7%  
Number of MUXCYs used 80 2,860 2%  
Number of LUT Flip Flop pairs used 274      
    Number with an unused Flip Flop 139 274 50%  
    Number with an unused LUT 1 274 1%  
    Number of fully used LUT-FF pairs 134 274 48%  
    Number of unique control sets 29      
    Number of slice register sites lost
        to control set restrictions
120 11,440 1%  
Number of bonded IOBs 44 102 43%  
    Number of LOCed IOBs 44 44 100%  
    IOB Flip Flops 3      
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 5 16 31%  
    Number used as BUFGs 5      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 3 200 1%  
    Number used as OLOGIC2s 3      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 4.35      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent¿ù 4 4 18:02:14 2016046 Warnings (46 new)12 Infos (11 new)
Translation ReportCurrent¿ù 4 4 18:02:20 2016000
Map ReportCurrent¿ù 4 4 18:02:29 201603 Warnings (3 new)6 Infos (0 new)
Place and Route ReportCurrent¿ù 4 4 18:02:36 2016003 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrent¿ù 4 4 18:02:41 2016004 Infos (0 new)
Bitgen ReportCurrent¿ù 4 4 18:02:49 2016000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrent¿ù 4 4 18:15:41 2016
WebTalk Log FileCurrent¿ù 4 4 18:15:46 2016

Date Generated: 05/02/2016 - 19:22:39