DigitalWatch Project Status (04/02/2016 - 18:13:02) | |||
Project File: | DigitalWatch.xise | Parser Errors: | No Errors |
Module Name: | DigitalWatch | Implementation State: | Synthesized |
Target Device: | xc6slx9-3tqg144 |
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No Errors |
Product Version: | ISE 14.7 |
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33 Warnings (0 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice Registers | 97 | 11440 | 0% | |
Number of Slice LUTs | 183 | 5720 | 3% | |
Number of fully used LUT-FF pairs | 94 | 186 | 50% | |
Number of bonded IOBs | 37 | 102 | 36% | |
Number of BUFG/BUFGCTRLs | 3 | 16 | 18% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | ¿ù 4 4 10:35:20 2016 | 0 | 33 Warnings (0 new) | 4 Infos (0 new) | |
Translation Report | Out of Date | ¿ù 4 4 09:33:54 2016 | 0 | 0 | 0 | |
Map Report | Out of Date | ¿ù 4 4 09:34:10 2016 | ||||
Place and Route Report | Out of Date | ¿ù 4 4 09:34:18 2016 | 0 | 0 | 3 Infos (0 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Out of Date | ¿ù 4 4 09:34:23 2016 | 0 | 0 | 4 Infos (0 new) | |
Bitgen Report | Out of Date | ¿ù 4 4 09:34:32 2016 | 0 | 0 | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Out of Date | ¿ù 4 4 09:36:24 2016 | |
WebTalk Log File | Out of Date | ¿ù 4 4 09:36:29 2016 |