DigitalWatch Project Status (04/02/2016 - 18:13:02)
Project File: DigitalWatch.xise Parser Errors: No Errors
Module Name: DigitalWatch Implementation State: Synthesized
Target Device: xc6slx9-3tqg144
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
33 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 97 11440 0%
Number of Slice LUTs 183 5720 3%
Number of fully used LUT-FF pairs 94 186 50%
Number of bonded IOBs 37 102 36%
Number of BUFG/BUFGCTRLs 3 16 18%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent¿ù 4 4 10:35:20 2016033 Warnings (0 new)4 Infos (0 new)
Translation ReportOut of Date¿ù 4 4 09:33:54 2016000
Map ReportOut of Date¿ù 4 4 09:34:10 2016   
Place and Route ReportOut of Date¿ù 4 4 09:34:18 2016003 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportOut of Date¿ù 4 4 09:34:23 2016004 Infos (0 new)
Bitgen ReportOut of Date¿ù 4 4 09:34:32 2016000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of Date¿ù 4 4 09:36:24 2016
WebTalk Log FileOut of Date¿ù 4 4 09:36:29 2016

Date Generated: 05/03/2016 - 23:09:31