Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version1756540
date_generatedTue Jul 18 18:56:06 2017 os_platformWIN64
product_versionVivado v2016.4 (64-bit) project_id8a74fa06a97c42839f2d0199ab3b8198
project_iteration3 random_id7db1267d2aaf566c8212e69cc046baff
registration_id7db1267d2aaf566c8212e69cc046baff route_designTRUE
target_devicexc7a15t target_familyartix7
target_packageftg256 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-6700HQ CPU @ 2.60GHz cpu_speed2592 MHz
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
system_ram8.000 GB total_processors1

vivado_usage
java_command_handlers
addsources=1 autoconnecttarget=1 configurebitstream=1 fliptoviewtaskrtlanalysis=2
launchprogramfpga=3 newproject=1 openhardwaremanager=2 projectsettingscmdhandler=1
resetlayout=1 runbitgen=12 runschematic=4 savedesign=2
showview=8 viewtaskprogramanddebug=1 viewtaskprojectmanager=7 viewtaskrtlanalysis=3
other_data
guimode=3
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=6 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=5 carry4=36 fdce=60 fdpe=2
fdre=146 gnd=4 ibuf=6 lut1=105
lut2=104 lut3=49 lut4=34 lut5=57
lut6=63 obuf=38 vcc=5
pre_unisim_transformation
bufg=5 carry4=36 fdce=60 fdpe=2
fdre=146 gnd=4 ibuf=6 lut1=105
lut2=104 lut3=49 lut4=34 lut5=57
lut6=63 obuf=38 vcc=5

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified]
results
cfgbvs-1=1 plck-12=3

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
results
timing-17=212

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -l=default::[not_specified] -name=default::[not_specified] -no_propagation=default::[not_specified]
-return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified] -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") confidence_level_clock_activity=Low confidence_level_design_state=High
confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=Low confidence_level_overall=Low
customer=TBD customer_class=TBD devstatic=0.486018 die=xc7a15tftg256-1
dsp_output_toggle=12.500000 dynamic=94.201243 effective_thetaja=4.9 enable_probability=0.990000
family=artix7 ff_toggle=12.500000 flow_state=routed heatsink=medium (Medium Profile)
i/o=90.545844 input_toggle=12.500000 junction_temp=125.0 (C) logic=1.704658
mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000
mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000
netlist_net_matched=NA off-chip_power=0.000000 on-chip_power=94.687260 output_enable=1.000000
output_load=5.000000 output_toggle=12.500000 package=ftg256 pct_clock_constrained=1.000000
pct_inputs_defined=0 platform=nt64 process=typical ram_enable=50.000000
ram_write=50.000000 read_saif=False set/reset_probability=0.000000 signal_rate=False
signals=1.950738 simulation_file=None speedgrade=-1 static_prob=False
temp_grade=commercial thetajb=8.2 (C/W) thetasa=4.6 (C/W) toggle_rate=False
user_board_temp=25.0 (C) user_effective_thetaja=4.9 user_junc_temp=125.0 (C) user_thetajb=8.2 (C/W)
user_thetasa=4.6 (C/W) vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 vccadc_total_current=0.020000
vccadc_voltage=1.800000 vccaux_dynamic_current=3.317251 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000
vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000 vccaux_static_current=0.053387 vccaux_total_current=3.370639
vccaux_voltage=1.800000 vccbram_dynamic_current=0.000000 vccbram_static_current=0.009934 vccbram_total_current=0.009934
vccbram_voltage=1.000000 vccint_dynamic_current=3.675396 vccint_static_current=0.340686 vccint_total_current=4.016082
vccint_voltage=1.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000
vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000
vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000
vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000
vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000
vcco25_voltage=2.500000 vcco33_dynamic_current=25.622665 vcco33_static_current=0.001000 vcco33_total_current=25.623665
vcco33_voltage=3.300000 version=2016.4

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=5 bufgctrl_util_percentage=15.63
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=45 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=25 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=50 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=25 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=5 carry4_functional_category=CarryLogic carry4_used=36
fdce_functional_category=Flop & Latch fdce_used=62 fdpe_functional_category=Flop & Latch fdpe_used=2
fdre_functional_category=Flop & Latch fdre_used=148 ibuf_functional_category=IO ibuf_used=6
lut1_functional_category=LUT lut1_used=11 lut2_functional_category=LUT lut2_used=104
lut3_functional_category=LUT lut3_used=49 lut4_functional_category=LUT lut4_used=34
lut5_functional_category=LUT lut5_used=57 lut6_functional_category=LUT lut6_used=63
obuf_functional_category=IO obuf_used=38
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=10400 lut_as_logic_fixed=0 lut_as_logic_used=216 lut_as_logic_util_percentage=2.08
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=20800 register_as_flip_flop_fixed=0 register_as_flip_flop_used=212 register_as_flip_flop_util_percentage=1.02
register_as_latch_available=20800 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=10400 slice_luts_fixed=0 slice_luts_used=216 slice_luts_util_percentage=2.08
slice_registers_available=20800 slice_registers_fixed=0 slice_registers_used=212 slice_registers_util_percentage=1.02
fully_used_lut_ff_pairs_fixed=1.02 fully_used_lut_ff_pairs_used=25 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0
lut_as_logic_available=10400 lut_as_logic_fixed=0 lut_as_logic_used=216 lut_as_logic_util_percentage=2.08
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0 lut_as_shift_register_used=0 lut_ff_pairs_with_one_unused_flip_flop_fixed=0 lut_ff_pairs_with_one_unused_flip_flop_used=48
lut_ff_pairs_with_one_unused_lut_output_fixed=48 lut_ff_pairs_with_one_unused_lut_output_used=45 lut_flip_flop_pairs_available=10400 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=76 lut_flip_flop_pairs_util_percentage=0.73 slice_available=8150 slice_fixed=0
slice_used=94 slice_util_percentage=1.15 slicel_fixed=0 slicel_used=68
slicem_fixed=0 slicem_used=26 unique_control_sets_used=26 using_o5_and_o6_fixed=26
using_o5_and_o6_used=102 using_o5_output_only_fixed=102 using_o5_output_only_used=0 using_o6_output_only_fixed=0
using_o6_output_only_used=114
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=692172 bogomips=0 bram18=0 bram36=0
bufg=0 bufr=0 ctrls=26 dsp=0
effort=2 estimated_expansions=306714 ff=212 global_clocks=5
high_fanout_nets=0 iob=44 lut=217 movable_instances=624
nets=723 pins=3298 pll=0 router_runtime=0.000000
router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a15tftg256-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -shreg_min_size=default::3 -top=DigitalWatch
-verilog_define=default::[not_specified]
usage
elapsed=00:00:26s hls_ip=0 memory_gain=404.703MB memory_peak=616.254MB